Small MPS resizes get faster when copies stay on one compute path
By OnTheRice · Sources and limitations · Report a correction
PyTorch changed small Apple-silicon storage resizes from a blit path that repeatedly switched and committed command encoders to its existing contiguous byte-copy compute kernel. On one M5 Pro, 4 KB to 1 MB microbenchmarks became about four to seven times faster, while gains above 4 MB were small. This matters most for allocation-heavy workloads with many tiny copies. The patch is unreleased and has no end-to-end model result. Watch release inclusion and tests across older Apple chips.
Source confidenceNot assessed
What’s changing?
A blit encoder adds fixed setup, switch and commit costs. The compute copy kernel reuses the active command path, so tiny copies avoid paying that cost on every resize.
Key points
- PyTorch commit 2ed02ea42af6e57d39f3e65f4b981f198f8c7548 routes MPS device-to-device resize copies through contiguous_byte_copy instead of opening a blit encoder for every call.
- The pull request reports M5 Pro microbenchmarks improving from 18.3 to 2.8 microseconds at 4 KB, 17.0 to 3.1 at 64 KB, and 18.1 to 4.4 at 1 MB.
- The same benchmark reports only 1.03x to 1.10x improvement from 4 MB to 256 MB, so the effect is concentrated in small copies.
What could change this view?
- The evidence is one M5 Pro microbenchmark and one resize operation. It does not show an end-to-end training or inference gain, and the patch is not in PyTorch v2.14.1.
Bottom line
Teams running allocation-heavy PyTorch work on Apple silicon have a concrete small-copy latency improvement to test. Large-copy behavior is nearly unchanged.
This is based on the information recorded with this signal.
How likely is this call? · Three frameworks
This signal has no investible bullish or bearish call. A market-direction percentage does not apply.
Evidence behind this view
Checks whether separate pieces of evidence support the same view.
Recorded connection
A blit encoder adds fixed setup, switch and commit costs. The compute copy kernel reuses the active command path, so tiny copies avoid paying that cost on every resize.
We have not established a separate count of independent evidence clusters for this card. Several reports may rely on the same event or data provider.
What past price moves show
Compares today’s price moves with recorded past patterns.
This card has no recorded investible call. A price-pattern comparison is not applicable unless a specific asset is added with evidence.
Evidence against this view
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Recorded opposing evidence and risks
The evidence is one M5 Pro microbenchmark and one resize operation. It does not show an end-to-end training or inference gain, and the patch is not in PyTorch v2.14.1.
Why the direction changed
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No documented bullish-to-bearish or bearish-to-bullish change is available for this card. We keep the original call and its time unchanged.
What people say vs the facts
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How past forecasts performed
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Sources, original wording and price checks
Published
First published through Sites 07 Oct 2026, 06:28:12 SGT
No explicit investible BULLISH or BEARISH call on this card.
What changed
Recorded public historyPyTorch changed small Apple-silicon storage resizes from a blit path that repeatedly switched and committed command encoders to its…
This is the first recorded public view. Further public updates will appear here.
- Small MPS resizes get faster when copies stay on one compute path
PyTorch changed small Apple-silicon storage resizes from a blit path that repeatedly switched and committed command encoders to its existing contiguous byte-copy compute kernel. On one M5 Pro, 4 KB to 1 MB microbenchmarks became about four to seven times faster, while gains above 4 MB were small. This matters most for allocation-heavy workloads with many tiny copies. The patch is unreleased and has no end-to-end model result. Watch release inclusion and tests across older Apple chips.
First published by OTR: 7 Oct, 06:28 SGTPublished by OTR: 7 Oct 2026, 06:28 SGT
Why the view changed
This is the first recorded view. Future source-backed updates will appear here.
Evidence, memory & review 2 linked sources
Named assets or actors: PyTorch MPS backend, Apple silicon, M5 Pro
Directional takeaway: N/A. This is an engineering signal, not an investible call. NO ENTRY.
OTR reasoning: A blit encoder adds fixed setup, switch and commit costs. The compute copy kernel reuses the active command path, so tiny copies avoid paying that cost on every resize.
Counterpoint: The evidence is one M5 Pro microbenchmark and one resize operation. It does not show an end-to-end training or inference gain, and the patch is not in PyTorch v2.14.1.
Source-grounded facts (paraphrased)
- Time not supplied: PyTorch commit 2ed02ea42af6e57d39f3e65f4b981f198f8c7548 routes MPS device-to-device resize copies through contiguous_byte_copy instead of opening a blit encoder for every call. Source record: source-1
- Time not supplied: The pull request reports M5 Pro microbenchmarks improving from 18.3 to 2.8 microseconds at 4 KB, 17.0 to 3.1 at 64 KB, and 18.1 to 4.4 at 1 MB. Source record: source-2
- Time not supplied: The same benchmark reports only 1.03x to 1.10x improvement from 4 MB to 256 MB, so the effect is concentrated in small copies. Source record: source-2
Source trail
- PyTorch commit 2ed02ea42af6e57d39f3e65f4b981f198f8c7548 ↗PyTorch on GitHub2026-10-06T21:38:33Z · published (UTC)
- PyTorch pull request 199689 and M5 Pro resize benchmark ↗PyTorch on GitHub2026-10-06T21:38:33Z · published (UTC)
Review status: PASS WITH NARROW M5 PRO MICROBENCHMARK LIMITS
No score or probability is presented.